VLSI Verification Engineer
EROS Technologies Inc.
Apply to this jobEROS Technologies was founded with a simple motive of offering the clients exactly what they want, how they want and when they want it. By leveraging for its clients its technological edge and right-sourcing advantage, EROS in a short period of time has grown to become one of the most trusted strategic technology partners. Treating every client as the top priority, we customize our solutions and services to align with the unique needs of each client.
Job Title: VLSI Verification Engineer
Location: Santa Clara, CA
Duration 6 Month Contract
Job description:
Verification engineers – OVM/UVM is Mandatory
CPU subsystem/DDR/Modem verification
All your information will be kept confidential according to EEO guidelines.
Summary
Verify CPU subsystem, DDR, and modem using OVM/UVM in VLSI design
Job title
VLSI Verification Engineer
Experience level
not specified
Industry
technology
Location requirements
Santa Clara, CA, on-site only
Salary
Not specified
Management role
No
Required skills
Preferred skills
Specializations
Structured locations inferred from the posting.
Santa Clara, CA, USA