Verification Engineer Onsite

Rootshell Enterprise Technologies

Apply to this job
Santa Clara, CA, us on site Until 8/21/2026 H-1B sponsor history First posted March 26, 2025 Last posted March 26, 2025
Job description

Rootshell has over 12 years of experience in Infrastructure Management Services and over 5 years of experience in providing contingent workforce management services to our clients across India with a highly effective process for recruiting, screening, testing and consultant management. Many of our clients regularly seek our advice when making changes to their internal IT staffing and vendor management programs. Over the years, we have formulated strategies, process and in-house IT Systems - enabling our sourcing engine to mature into one of the strongest providers in the country.

We need 2 on site USA, 20 Engineers in India/Korea. Out of 20 - 5 should be Lead Engineers where they are willing to go Korea, on site (we will take care of Visa from India) - 15 will be working from India.
This is for ASIC/SOC Verification Engineers
Must to have skills:

Minimum 5 yeas experiance as Veification Engineer
System Verilog, UVM or OVM methodologies block level verification atleast 2 years.
Additional skill and not mandatory
SVA (systemverilog assertions), modem baseband verification experience, AHB, AXI or memory controller, arm based assembly testings, arm performance or bus performance

A successful DV candidate will be detail oriented with solid analytic and debugging skills, strong knowledge of digital design, good understanding of Object Oriented Programming (OOP) concepts and fine written and verbal communication skills.
Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and such as Verilog, SystemVerilog and VHDL is preferred.
SOC Design Verification (ARM, AMBA, AHB, AXI, Peripherals, clock, security)
Modem Design Verification (LTE, WCDMA, UMTS, CDMA,DSP or data path verification
Low-Power Design Verification
Tools used are : Verdi , VCS, IUS

Certification would be given preference

About this role

Summary

Verify ASIC/SOC designs using SystemVerilog, UVM, and related methodologies on-site.

Job title

Verification Engineer Onsite

Experience level

5+ years

Industry

technology

Location requirements

Onsite in Santa Clara, CA; remote not allowed

Salary

Not specified

Visa sponsorship

H-1B sponsor history

Management role

No

Skills & keywords

Required skills

SystemVerilogUVMverificationdigital designVerdiVCS

Preferred skills

SVAmodem verificationARMAMBAAXIlow-power verificationVHDL

Specializations

ASIC verificationSOC verificationSystemVerilogUVMVHDL
Locations

Structured locations inferred from the posting.

Santa Clara, CA, USA

On-site City