Systems Verification & Concurrent Kernel Architecture Research Intern

The Challenge: The "Logic-to-Silicon" Gap

Roles and Responsibilities

• Design Logic (TLA+/Spin): Formalize locking protocols to mathematically prove the absence of deadlocks and circular waits.
• Implementation Audit (ESBMC/CBMC): Apply Bounded Model Checking to C source code to exhaustively scan for data races, pointer safety, and invariant violations.
• Hardware Mapping: Verify the placement of memory barriers to prevent hardware-level synchronization failure on modern CPUs.
• AI-Augmented Scaling: Leverage LLMs as an "Inference Engine" to synthesize formal invariants and environment harnesses, then critically audit the results for logical soundness.

Qualifications

• Currently pursuing or completed a PhD or Master’s degree in Computer Science, Computer Engineering, Applied Mathematics, or a related field with relevant research projects and publications.
• Low-Level Systems Mastery: Deep proficiency in C; ability to reason about memory alignment, volatile keywords, and hardware interrupts. You should be comfortable reading ARMv8 assembly to ensure compiler optimizations haven't compromised synchronization.
• Concurrent Intuition: A visceral understanding of L1/L2 cache coherency (MESI), lock hierarchies, and why a "correct" C program can fail on weak-memory hardware if barriers are missing.
• Formal & Logical Rigor: The ability to model software as a discrete state-machine. You should prefer a "proof of absence" (no bugs exist) over a "proof of presence" (one test passed).
• The Researcher's Grit: Persistence in the face of "state space explosion" or cryptic model-checker errors. You must be a detective capable of pruning models to find one-in-a-billion interleaving failures.