Staff Engineer Verification

Job Description
In your new role you will:

• Will be part of a team that handles Verification for complex SoCs and close the Verification to the challenging milestones.
• SoC Verification: Full-chip VR creation as per the chip requirements and UVM/OVM Test benches creation
• Support in building verification infrastructure at the chip level asper the requirements
• Capable of handling multiple areas of SoC Verification: RTL, Power Aware and Gate Level Verification

Your Profile
You are best equipped for this task if you have:

• Bachelor's - 6 to 7 years’ experience, Master’s - 5 to 6 years’experience
• Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM.
• Experience and knowledge in Verification of SoCs related to different applications.
• Good Knowledge in Power aware verification and Gate level verification is preferable. 
• Should be able to understand the Full-chip Verification requirements well and good knowledge in industry standard protocols is a plus

Contact:
    [email protected]

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