Staff Engineer Digital Design - Mixed Signal IPs (f/m/div)

Are you passionate about digital design and mixed-signal IP development? Do you want to be part of a team who generate synergies across Infineon applications through AMS Solutions? Are you eager to collaborate with a world-class team of engineers in a dynamic and innovative environment? Then our Design Enabling & Services team in Padova is waiting for you!

Job Description
As a Digital Design Engineer, you will be specialized in the design and development of mixed-signal IPs for ASICs. Furthermore, you will also have the opportunity to work on cutting-edge projects, collaborating with a talented team of engineers to deliver high-quality IP solutions.

In your new role you will:

• Design, develop, and verify digital components of mixed-signal IPs for ASICs
• Write and maintain SystemVerilog code for digital IP blocks, including RTL design, simulation, and synthesis
• Collaborate with analog designers to ensure seamless integration of digital and analog components
• Develop and execute verification plans, including writing testbenches and assertions
• Perform simulation, synthesis, and place-and-route tasks using industry-standard tools
• Debug and optimize digital IP blocks to meet performance, power, and area requirements
• Work closely with the verification team to ensure IP quality and reliability
• Participate in design reviews and contribute to the improvement of design processes and methodologies

Your Profile
You have excellent problem-solving skills, with the ability to debug complex digital designs. Your strong communication and collaboration skills allow you to work effectively in a team environment. You are also detailed oriented, able to manage multiple tasks, and adapt to evolving project requirements.

You are best equipped for this task if you have:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or similar field of study
• At least 3 years of experience in digital design, with a focus on mixed-signal IPs
• Proficiency in System Verilog, with experience in writing RTL code and testbenches
• Strong understanding of digital design principles, including logic design, timing analysis, and clock domain crossing
• Experience with industry-standard design tools, such as simulators, synthesizers, and place-and-route tools
• Fluency in English (mandatory)

It is an advantage if you have:

• Experience with Spyglass, LEC, Synthesis, and ATPG tools
• Knowledge of low-power design techniques and power management strategies
• Familiarity with scripting languages, such as Perl or Python
• Experience with version control systems, such as Git, Perforce
• Understanding of analog-digital interface design principles and mixed-signal design flows
• Understanding and design of digital filter principles

Please send us your CV in English.



Contact:
    Rita Costa, LinkedIn

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