STA Engineer

Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables.

Description

As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. You will be working with other specialists that are members of the SoC Design, SoC Design Verification, DFT, Architecture and Physical Design teams. Working with CAD and Flow teams to define and improve front-end design methodologies. Develop and maintain methodology and flows related to timing analysis.

Minimum Qualifications

Bachelors Degree + 0 Years of Experience.

Preferred Qualifications

Strong fundamentals in the area of Digital design
Familiarity with ASIC design timing concepts
Proficient in scripting languages (TCL, Python and Perl)
Exposure to STA tools (Primetime) , writing timing constraints and knowledge of timing corners / modes is a plus
Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks
Self-starter and highly motivated
Ability to communicate optimally across all internal groups