Sr Principal Design Engineer

CZ61 NXP Semiconductors Czech Republic s.r.o.

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Noida Until 8/21/2026 H-1B sponsor history First posted June 16, 2026 Last posted June 16, 2026
Job description

Generic Job Description (not Job Level specific): The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design. The individual is responsible from RTL synthesis to GDS implementation and optimization of design including floorplanning, routing, timing convergence (STA) including related design ECO and physical verification for fulfilling all Technology & reliability related rules, such as DRC/LVS/Electromigration/IR drops. The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.


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About this role

Summary

Design and optimize physical implementation of ICs from RTL to GDSII.

Job title

Sr Principal Design Engineer

Experience level

senior level

Industry

technology

Location requirements

On-site in Noida, India; no remote work allowed.

Salary

Not specified

Visa sponsorship

H-1B sponsor history

Management role

No

Skills & keywords

Required skills

RTL synthesisfloorplanningroutingtiming analysisphysical verification

Preferred skills

None specified

Specializations

physical designRTL synthesisGDS implementationfloorplanningtiming convergence
Locations

Structured locations inferred from the posting.

Noida, Uttar Pradesh, India

On-site City