Sr Principal Design Engineer
CADENCE US
Apply to this jobAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently
Should be good in Perl/Tcl scripting and automation
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Summary
Design verification, test-bench development, project management, scripting, and automation in VLSI.
Job title
Sr Principal Design Engineer
Experience level
12-14 years
Industry
software
Location requirements
Bangalore, on-site work only
Salary
Not specified
Management role
No
Required skills
Preferred skills
Specializations
Structured locations inferred from the posting.
Bengaluru, Karnataka, India