Sr. FPGA Design Engineer

Current Openings

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Dallas, TX Until 8/22/2026 First posted March 18, 2026 Last posted March 18, 2026
Job description

About Talent 101 Inc

Talent 101 is an Engineering and IT services provider, with clients that range from start-up to Fortune 500. We specialize in solutions for the Semiconductor, Automotive, Electronics, Energy, Telecom, and Defense industries.

About the role

We have are adding a Sr. FPGA Engineer to our design team that has experience taking RTL to synthesis; this role is onsite in Dallas, TX full time for us wiht 401k, pto, medical, etc.

What you'll do

  • RTL File is provided for enhancement
  • Responsible to Synthesize and implement all the logic in Vivado to complete FPGA emulation
  • After Synthesis and Implementation will be responsible for executing and turn over .bit file
  • Will also be converting blocks (Buck/boost, Charge Pumps, register)
  • Synthesis tool preferably Synplify Premier (but any synthesis tool should work)
  • Test sequence development in Vivado
  • Knowledge of eUSB protocol , SPMI, SPI, I2C
  • Perform simulations based on Verification teams test benches to make sure the communication happens. This would be the step prior to generating a bit stream to test in the lab.
  • Requires good team skills and ability to work across multiple teams cohesively.


Talent101 pays referral fees.

Applicants must be at least 18 years or older, must be willing to take a drug test and background check as part of the selection process and must have legal authorization to work in the United States.

Talent 101 is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to protected characteristics, including race, color, religion, sex, national origin, disability, veteran status, sexual orientation, gender identity or age.

About this role

Summary

Design, synthesize, and verify FPGA logic using Vivado and RTL files.

Job title

Sr. FPGA Design Engineer

Experience level

senior level

Industry

semiconductor

Location requirements

onsite in dallas, tx, no remote work allowed

Salary

Not specified

Management role

No

Skills & keywords

Required skills

RTLVivadosynthesisFPGAsimulation

Preferred skills

eUSB protocolSPMISPII2C

Specializations

RTLFPGAsynthesisVivadoverification
Locations

Structured locations inferred from the posting.

Dallas, TX, USA

On-site City