Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

US, CA, Cupertino Until 10/5/2026 First posted August 6, 2026 Last posted August 6, 2026
About this role

Summary

Designing ASICs for machine learning acceleration in cloud-based environments.

Job title

Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

Experience level

senior level

Industry

technology

Location requirements

must be in USA, remote work allowed

Salary

Not specified

Management role

No

Skills & keywords

Required skills

asic designvhdl/verilogc/c++chip architecture

Preferred skills

None specified

Specializations

asic designmachine learningcloud-scale
Locations

Structured locations inferred from the posting.

Cupertino, CA, USA

Remote City