SoC Physical Design Engineer, PnR

Austin Until 10/7/2026 0+ years exp First posted August 8, 2026 Last posted August 8, 2026
Job description

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC applying innovative process technology.

Description

In Physical Design, you will be at the center of design effort collaborating with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs Knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would include:
- Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
- Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
- Timing, physical and electrical verification, and driving the signoff closure for the partitions.
- Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.

Minimum Qualifications

Minimum BS Degree with 0+ years experience
Basic understanding of logic gates.

Preferred Qualifications

Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.
Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields.
Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE.

About this role

Summary

Designs and implements physical partitioning and routing for complex SOCs, ensuring design goals.

Job title

SoC Physical Design Engineer, PnR

Experience level

entry level

Minimum experience

0+ years exp

Industry

technology

Location requirements

Austin, on-site work only

Salary

Not specified

Management role

No

Skills & keywords

Required skills

basic chip architecturephysical synthesisnetlist to GDS2timing (STA)DRC/LVSVerilogVHDLPythonPerlTCL

Preferred skills

computer architectureVLSIlogic designcircuit designteamwork

Specializations

physical designplace and routetimingverificationVLSI
Locations

Structured locations inferred from the posting.

Austin, TX, USA

On-site City