SoC Physical Design Engineer, Electrical Analysis

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! As a Physical Electrical Analysis Engineer on our SoC team, you will be driving the electrical analysis and verification of an SoC.

Description

- As a senior member of our SoC physical design team, you will be performing various electrical analyses at the block or chip level, including but not limited to: Gridcheck, ESD, Static/Dynamic IR, EM, Noise and Signal EM.
- You will collaborate with the CAD/library/circuit technology/system teams for tech/flow evaluation, bring-up, validation and qualification for SoC chip development.
- You will also work with the implementation team during the entire chip design cycle to drive EMIR test planning, analysis support, and sign-off closure for tape-out.
- You will manage schedules and support cross-functional engineering efforts for the success of Apple’s SoC product development.

Minimum Qualifications

Minimum BS and 10+ years of relevant industry experience
Knowledge of low-power circuit design, computer architecture, and/or digital systems.

Preferred Qualifications

Experience with industrial EDA backend tools including Redhawk, PrimeRail, Voltus.
Experience with ASIC or AMS physical implementation and analysis flow for IP blocks as well as SoC fullchip.
Proficient in automating and debugging verification flows for digital VLSI design.
Experience with Innovus, Design Compiler, PrimeTime and Tempus.
Familiar with voltage drop budgeting, low-power design techniques, and sign-off criteria for solid-state digital circuit systems.
Experience in multiple design tape-outs regarding power integrity signoff.
Circuit design background and SPICE experience.