Senior Static Timing Engineer

About the Job

As a Static Timing Engineer on the chip implementation team, you will work on the physical implementation of ASICs using advanced technology nodes. You will work on constraint development and validation, and timing closure of large, complex high performance compute ASICs. You will develop static timing methodologies, margins, automation scripts, and write documentation. You will perform technical evaluations of vendors, tools, methodologies, and will provide recommendations. Additionally, you will work with architecture, logic design, and DFT teams to understand and implement their requirements.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Perform full chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs.
• Debug and resolve common STA or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations.
• Develop timing constraint and verify it for sign-off.
• Utilize Perl, Python, Tcl, or Bash to create static timing flow automation scripts.
• Own and maintain Primetime STA flows.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with static timing analysis.
• Experience in Primetime or Tempus Tcl scripting and static timing analysis debug.
• Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience writing, reviewing and verifying complex Tcl constraints for static timing analysis.
• Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
• Experience working with multiple foundries.
• Knowledge of semiconductor device physics and transistor characteristics.