Senior Staff Engineer Verification

Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -Partial

In your new role you will:

• Behavioral modeling: Verilog, Wreal or SV-RNM -Full
• AMS Verification for SoC or IPs -Full
• Test plan preparation as per the dynamics of product specifications - Full
• Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -Partial
• Testcase Debug & proposing new scenarios - Partial
• Handling project dynamics on scope, schedule and effort – coming up with alternative verification plans- Full
• Self-motivated to drive new scope expansion proposals mapping to business value
• Mentoring junior engineers in creating problem solving mindset
• Establishing cross collaboration with other domains and coming up with proposals in enhancing product development working approaches

You are best equipped for this task if you have:

• Bachelors with 9+ years of experience
• Mentoring: Technical mentoring for junior engineers. Instigate thought-provoking culture.
• Analog: Functional spec understanding of standard power management blocks, clock circuits, and data converters. Loop analysis is an added advantage
• HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage
• Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS
• Automation: Perl/python/shell
• Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements

Contact:
    [email protected]

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