Senior Staff Engineer Verification

Good understanding of analog circuits and ability to write analog/RNMbehavioral models using verilog/verilogA/verilog-AMS/SV-RNM.

Job Description
In your new role you will:

• Minimum 5+ Years of experience in Analog & mixed signal verification domain.
• Good understanding of analog circuits and ability to write analog/RNMbehavioral models using verilog/verilogA/verilog-AMS/SV-RNM.
• Ability to develop AMS test plan, implement TB components, integrate spice netlists, develop checkers, assertions, coverage, and debuggingAMS simulations.
• Interact with Analog, RTL & DV teams to bring up system level scenarios in AMS environment.
• Efficient working knowledge on EDA tools/simulators (Cadence -virtuoso schematic editor, Xcelium,APS/XPS OR Synopsys – VCS, CustomsimOR Siemens - Questa, Eldo).
• Provide support to characterization teams during post-siliconvalidation.
• Domain knowledge on power and analog building blocks like reference,comparator, op-amp, current mirror, charge pump, linera regulator andswitching regulator.
• Strong interest and understanding of Design and verification methodologies (OVM/UVM).
• Self-motivated to work effectively & incorporate next generation AMS methodologies.

Your Profile
You are best equipped for this task if you have:

• A Bachelor or Master’s Degree in Electrical/Electronic Engineering or equivalent field of studies;
• Experience in analog and mixed-signal verification in CMOS and Power Technologies;
• Good Analytical skills and very good understanding of Analog and digital building blocks
• Familiarity with modelling and verification of power conversion, such as DC DC converters, is added advantage;
• Experience in Python, Perl, Shell scripting is added advantage
• Experience in post silicon debug ;
• Proficiency in computer-aided design tools and methodologies;

Contact:
    [email protected]

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