Senior Staff Engineer

The role will own verification of one or more IP blocks at IP-level andleading to chip-level for USB and automotive applications.

In your new role you will:

• The role will own verification of one or more IP blocks at IP-level andleading to chip-level for USB and automotive applications.

• The role will be responsible for Testbench Architecture, Test planning,Test Development and Verification for IP Blocks and Subsystems.

• The role will work on verification closure, including test plan,coverage and assertion closure.

• The role will Interact with other functional leads from Design, FW/SW,Validation Teams.

• The role will evaluate new tools & methodologies required forcontinuous improvement of design flows.

• Guide & Mentor junior engineers working on IP Blocks, Subsystem.

You are best equipped for this task if you have:

• Bachelors/Masters in Electrical/Electronics Engineering with 8+ yearsof experience in

• Advanced user of System Verilog & UVM for IP , Subsystem, SOC levelverification

• Exposed to Coverage Driven & Constraint random Verification

• Experience with Assertion based & Formal Verification

• Experience with low power design aspects , Power Aware Verification(UPF) and Gate level

• Experience in verification of designs in RTL & GLS

• Experience in developing verification architecture

• Experience in leading a team, create & execute test plan, Coverageclosure

Contact:
    [email protected]

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