Senior Staff Elect Design Engineer

Expertise to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the vectors, verification, an

In your new role you will:

• ASIC flow understanding.
• The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the vectors, verification, and Post silicon debug.
• In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies.
• The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
• Scripting skills such as PERL/TCL/Python are preferred. 

You are best equipped for this task if you have:

•  8+ years of experience as Verification engineer.
• Knowledge of System Verilog.
• Experience with SOC level verification
• Experience in Tester failure debugs
• Excellent analytical and debugging skills.
• Basic knowledge in design techniques Verilog or VHDL
• A good knowledge of simulation flow
• UVM knowledge a plus
• Perl basics a plus

Contact:
    [email protected]

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