Senior SoC Design Verification Engineer, Google Cloud

About the Job

In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
• Identify and write all types of coverage measures for corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of experience with creating and using verification components and environments in standard verification methodology.
• Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, or a related field.
• 3 years of experience with creating and using verification components and environments in standard verification methodology.
• Experience with verification techniques, and the full verification life cycle.
• Experience with performance verification of ASICs and ASIC components.
• Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
• Experience in four or more System on a chip (SOC) cycles.