Senior SoC Design Verification Engineer

Altera Corporation

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Regus, Madhapur Until 8/21/2026 10+ years exp First posted May 19, 2026 Last posted May 19, 2026
Job description

Job Details:

Job Description:

Job Description:

As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.

Responsibility

  • Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.
  • Create testcase and testbench with UVM methodology
  • Fullchip/system functional verification, by defining verification strategies/methodology​​ and test plan to enable effective verification
  • Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
  • Experience on Emulation will be an add on.

    Qualifications:

    Qualifications:

    • 10+ years of experience with complex ASIC designs and/or verification
    • Familiar with System Verilog language
    • Experience on UVM verification methodology, and formal verification method
    • Working knowledge of scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.
    • Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.
    • Experience with ARM and RISC Debug Architectures is desired with focus on design verification.
    • Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.
    • Strong communication skills and the ability to work with a team spread across different geography sites
    • Flexible in dynamic environment

    Job Type:

    Regular

    Shift:

    Shift 1 (India)

    Primary Location:

    Regus, Madhapur

    Additional Locations:

    Posting Statement:

    All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
    About this role

    Summary

    Verify SoC design using UVM methodology, create test plans, coordinate cross-functional teams

    Job title

    Senior SoC Design Verification Engineer

    Experience level

    10+ years

    Minimum experience

    10+ years exp

    Industry

    software

    Location requirements

    Madhapur, India, on-site work only

    Salary

    Not specified

    Management role

    No

    Skills & keywords

    Required skills

    SystemVerilogUVMverificationLinux/Unix scriptingPerlPythondebug architecture

    Preferred skills

    EmulationARMRISCUltraSoCTessent

    Specializations

    verificationUVMASICfull chip verification
    Locations

    Structured locations inferred from the posting.

    Madhapur, Odisha 759125, India

    On-site City