Senior Mask Design Engineer - Hardware

Taiwan, Hsinchu Taiwan, Taipei Until 9/20/2026 5+ years exp First posted July 22, 2026 Last posted July 22, 2026
Job description

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to take on, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. We would love to hear from you!

We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for contributing to our latest generation chiplet interface projects

What you'll be doing:

  • Performing physical layout for mixed-signal functions like top level, high speed datapaths and high-speed clocking designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.

  • You'll work closely with mixed-signal design engineers to customize designs for integration in VLSI products.

  • Take part in floor planning, custom layout and verifying against design rules and schematics.

What we need to see:

  • Have a BSEE or equivalent experience. Minimum of 5+ years industry experience in Mask and Layout Design.

  • Working independently on creating layout with excellent quality

  • Deep understanding and previous experience for FinFET technology is a must

  • You are an authority with Cadence custom circuit design tools - particularly virtuoso.

  • Able to handle fast-paced project and iterate quickly based on designer’s feedback

  • You can work effectively in a team, good interpersonal skills, enthusiasm, and positive energy.

  • Scripting languages like perl, python, skill etc.is a plus

  • Should have knowledge of DRC and LVS checking flows, ability to customize decks.

#LI-Hybrid

About this role

Summary

Perform physical layout for high-speed mixed-signal functions in advanced CMOS technologies.

Job title

Senior Mask Design Engineer - Hardware

Experience level

5+ years

Minimum experience

5+ years exp

Industry

software

Location requirements

Hsinchu or Taipei, Taiwan; hybrid work allowed

Salary

Not specified

Management role

No

Skills & keywords

Required skills

cadence virtuosomask layoutdrclvsfinfet

Preferred skills

perlpythonskill

Specializations

mask layoutCMOSFinFETcadence virtuoso
Locations

Structured locations inferred from the posting.

Hsinchu, North District, Hsinchu City, Taiwan

Hybrid City

Taipei, Taiwan

Hybrid City