Senior FPGA Design Engineer

San Jose, CA, us on site Until 8/23/2026 5+ years exp H-1B sponsor history First posted May 21, 2026 Last posted May 21, 2026
Job description

Axiado is building the future of AIpowered digital infrastructure. We are a fastgrowing, wellfunded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AIdriven resilience and efficiency, and realtime platform management. Our technology protects the world’s most critical infrastructure—from data centers to nextgeneration cloud and AI platforms—by securing systems at the foundation levels of hardware, independent of host CPUs and operating systems. 

Founded in 2019 and now over 150 employees strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders, validating both our technology and our long-term market trajectory. Axiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company’s 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award. 

At Axiado, developing breakthrough technology takes more than great engineering—it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world. 

If you’re driven to innovate, energized by hard problems, and excited to help define the future of secure AI infrastructure, we invite you to apply and join us on this journey. 

Senior FPGA Design Engineer position is your opportunity to join one of the industry’s leading companies in platform security management and ransomware detection for cloud datacenters, 5G infrastructure and disaggregated compute ecosystems. You should have prior knowledge about RTL design, FPGA prototyping and computer architecture. As the Senior FPGA Design Engineer for Axiado, you will have the opportunity to work in design, verification, debug and system integration. You will work closely with the Architecture, Verification, ASIC Design and Software teams, and report into the Engineering organization. 

Key Responsibilities

  • RTL design for FPGA, including RTL porting, IP integration, closing timing and generating bit streams

  • FPGA simulation setup and testing

  • FPGA system setup, validation and debug

  • Work with SW team to bringup and validate FPGA system product

  • Product experience with FPGAs and related tools such as Vivado and Protocompiler

  • Strong experience in RTL design, especially design for FPGAs

  • Integration of IPs and CPUs for FPGA

  • Experience in RTL simulation testing

  • Experience in bringing up and debugging SW on FPGA systems

  • Familiarity with PCIe, USB, Ethernet, SPI. The following are pluses: ESPI, SGPIO, LTPI

  • Self-driven, good problem solving and communication skills

  • BS or MS (preferred) degree in EE/EECS/CS or equivalent. 

  • At least 5 years of industrial experience

Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

We are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are.

Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.

Compensation (from employer):
150000 – 200000 USD (YEARLY)

About this role

Summary

Design, verify, debug FPGA systems; collaborate with software and hardware teams.

Job title

Senior FPGA Design Engineer

Experience level

5+ years

Minimum experience

5+ years exp

Industry

semiconductor

Location requirements

San Jose, CA; remote work not specified

Salary

150000 – 200000 USD (YEARLY)

Visa sponsorship

H-1B sponsor history

Management role

No

Skills & keywords

Required skills

RTL designFPGA prototypingVivadoProtocompilerRTL simulationdebugging

Preferred skills

PCIeUSBEthernetSPIESPISGPIOLTPI

Specializations

RTL designFPGAverificationsystem integration
Locations

Structured locations inferred from the posting.

San Jose, CA, USA

On-site City