Senior Engineer

Job Description
In your new role you will:

• Create and define verification plans for SOC integration verification;
• Develop verification environments for our ICs using UniversalVerification Methodology (UVM).
• Develop test scenarios using SystemVerilog and SW based C/CPP tests.
• Utilise Perspec/PSS portable stimulus tooling to enable randomised SW based tests.
• Develop assertions in SystemVerilog for formal verification;
• Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies;
• Work closely with IP verification teams to align work split and information sharing.

Your Profile
You are best equipped for this task if you have:

• You have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline;
• You have at least two years of experience in Constrained-Random Metric-Driven Verification or SOC integration verification.
• You have capabilities and experience in working with microcontroller-based ICs, as well as security and safety requirements;
• You have good know-how with UVM especially using SystemVerilog.
• You have some knowledge of SW-based testing (writing/executing SW on embedded CPUs)
• Have knowledge of RTL design (System Verilog);
• Ideally have knowledge of working with Verification IPs (VIPs)

Contact:
    Gowri Shenoy, LinkedIn

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Are you in?

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