Senior Chip Design Verification Engineer

Israel, Tel Aviv Until 9/9/2026 5+ years exp First posted July 11, 2026 Last posted July 11, 2026
Job description

We are looking to hire a Chip Design Verification Engineer to join NVIDIA Chip Design group. The work environment is versatile, educational, dynamic and challenging as our employees are currently working on innovative, next-generation networking devices at the forefront of technology in terms of performance and power efficiency. Daily work involves all aspects of chip development: Design, Micro- Architecture, Firmware, and Verification. Work with the best and become one of the best! 

What you will be doing:

  • Work in a combined design and verification team which develops core units within the Networking silicon.
  • Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
  • Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

What we need to see:

  • B.SC./ M.SC. in Computer Engineering /Electrical Engineering/Communication Engineering or equivalent experience
  • 5+ years of proven experience in Design Verification.
  • Deep and vast experience with System-Verilog UVM.
  • Deep knowledge in HDL (Verilog/VHDL)
  • Familiarity with the different verification tools and methodologies.
  • High-Level English

Ways to stand out from the crowd:

  • Validated experience in ASIC Verification.
  • Knowledge in System-Verilog UVM

NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our Networking Silicon design team and help us build the next chip in this exciting and quickly growing field.

About this role

Summary

Design and verify chip components using System-Verilog UVM and HDL.

Job title

Senior Chip Design Verification Engineer

Experience level

5+ years

Minimum experience

5+ years exp

Industry

software

Location requirements

Tel Aviv, Israel; onsite preferred

Salary

Not specified

Management role

No

Skills & keywords

Required skills

system-verilogUVMverilogVHDLverification tools

Preferred skills

ASIC verificationsystem-verilog UVM

Specializations

chip designverificationsystem-veriloghdlverification tools
Locations

Structured locations inferred from the posting.

Tel Aviv-Yafo, Israel

On-site City