RFIC Layout Engineer

The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.

Description

As an RFIC Layout Designer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products. You will have a critical impact on developing Apple’s state-of-the-art radios and getting them into hundreds of millions of products.

Minimum Qualifications

5+ year minimum related experience required.
Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.
High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology.
Knowledge of Cadence layout tools.

Preferred Qualifications

Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.
Solid understanding of RC delay, electromigration, and coupling.
Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE.
Excellent communication skills and able to work with cross-functional teams.
Scripting skills in PERL or SKILL.