Principal RTL Design Engineer

STMicroelectronics

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Greater Noida, India Bangalore, India Until 9/21/2026 15+ years exp H-1B sponsor history First posted July 23, 2026 Last posted July 23, 2026
Job description

OUR STORY


At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.


When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.


Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo,  drive innovation, and unlock their own potential. 

Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.

Job Description:

As part of the Platform design team, the Design Engineer will be responsible for leading and contributing to the design and delivery of Core Subsystem across multiple SoC generations. With deep experience in RTL design and SoC-level integration, this role is critical for enabling high-performance, low-power, and functionally safe systems across diverse markets.

Responsibilities

  • Collaborate with systems architects and microarchitects to define high level, implementable SOC specifications.
  • Own end-to-end IP/Sub-system RTL delivery while analysing and optimising design for power, performance and area (PPA) targets.
  • Work on IPs including ARM Cores, Interconnect Fabrics, Memory Controller IPs.
  • Lead RTL design and integration of Sub-system supporting complex architectures with multi-core, multi-reset domains.
  • Demonstrate strong proficiency with frontend flows, including LINT, CDC, Synthesis, DFT and Static Timing Analysis (STA).
  • Drive the development of robust Safety, Security and Debug architectures for advanced SOCs with multiple interconnects.
  • Design and integrate standard interface protocols like AHB/AXI and memory interfaces like RAM, Flash.
  • Engage cross-functionally with DFT, Physical Design, Verification, Emulation and Validation teams to ensure first time right silicon and on-time project delivery.
  • Support silicon bring-up, debug, and post-silicon performance analysis through detailed simulation and system-level integration.
  • Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle.
  • Utilize scripting to manage design flows and automate repetitive tasks for improved efficiency. 
  • Mentor junior engineers, and provide technical leadership and guidance across multiple design projects. 
  • Contribute to the innovation quotient of the team via Patents, Industry standard publications etc.

Qualifications: 

  • Bachelor's or Master’s degree or equivalent experience in Electronics/Electrical Engineering with 15+ years of RTL design experience. 
  • Hands on experience in RTL coding, debugging, verification, synthesis and timing closure. 
  • Strong experience in ARM based SOC architecture and ASIC design flow
  • AMBA protocols (AXI, AHB, APB), clock/reset domains and memory sub-systems.
  • Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis.
  • Familiarity with formal verification techniques, static/dynamic power checks.
  • Proficiency in scripting and automation using Python.
  • Excellent leadership, communication skills.
  • Experience working with global cross-functional teams.
  • Working knowledge of safety-critical design flows in automotive systems. Knowledge of Automotive Functional Safety ISO26262 is a plus.

ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.

At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture. 


To discover more, visit st.com/careers.

About this role

Summary

Lead RTL and SoC design, integration, verification, and optimization for advanced chips

Job title

Principal RTL Design Engineer

Experience level

15+ years

Minimum experience

15+ years exp

Industry

semiconductor

Location requirements

Greater Noida or Bangalore, India; remote work not specified

Salary

Not specified

Visa sponsorship

H-1B sponsor history

Management role

No

Skills & keywords

Required skills

RTL codingARM architectureASIC flowAMBA protocolsscripting PythonEDA tools

Preferred skills

safety-critical designISO26262automotive safetyverification techniquessystem-level debug

Specializations

RTL designSoC architectureARM coresinterconnect protocolspower performance area
Locations

Structured locations inferred from the posting.

Greater Noida, Uttar Pradesh, India

On-site City

Bengaluru, Karnataka, India

On-site City