Principal Logic Design Engineer

Altera Corporation

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New Delhi, India (Remote) Bengaluru, Karnataka, India remote Until 8/21/2026 15+ years exp First posted March 18, 2026 Last posted March 18, 2026
Job description

Job Details:

Job Description:

Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We are driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance.

We are seeking a talented Logic Design Engineer to develop and optimize mixed-signal and high-speed IPs for integration into full-chip designs.

Key Responsibilities:

1. Participate in design development tasks throughout the IP development flow.

2. Develops the logic design, register transfer level (RTL) coding, and simulation for an IP.

3. Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.

4. Applies various strategies, tools, and methods to write RTL and optimize the logic to quality the design to meet the IP release requirement.

5. Involve in design example creation, simulation example creation, IP integration and release process.

6. Involve in IP design example brings up on hardware, hardware verification and failure debugging.

Qualifications:

1. 15+ years' experience with bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.

2. Experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis

3. Experience in programming with C/C++/Perl/Python/TCL/Unix Shell script

4. Experience in FPGA design and programming is a plus.

5. Experience in RTL validation is a plus.

6. Ability to work with different teams, good communication and problem-solving skills.

Job Type:

Regular

Shift:

Shift 1 (India)

Primary Location:

New Delhi, India (Remote)

Additional Locations:

Bengaluru, Karnataka, India

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
About this role

Summary

Develops and optimizes high-speed, mixed-signal IPs, RTL coding, and simulation.

Job title

Principal Logic Design Engineer

Experience level

15+ years

Minimum experience

15+ years exp

Industry

technology

Location requirements

New Delhi, India, or Bengaluru, India; remote allowed

Salary

Not specified

Management role

No

Skills & keywords

Required skills

System VerilogVCSSynthesisprogramming C/C++/Perl/Python/TCL/Unix Shell

Preferred skills

FPGA designRTL validation

Specializations

logic designRTLFPGAmixed-signalhigh-speed IPs
Locations

Structured locations inferred from the posting.

India

Remote Country

New Delhi, Delhi, India

On-site City

Bengaluru, Karnataka, India

On-site City