Principal Engineer Verification

In your new role you will:

• Define and implement verification concepts for complex SoCs usingstate-of-the-art methodologies such metric driven, formal andemulation-based verification as well as HW/SW co-verification
• Design the architecture of advanced testbenches using SV/UVM
• Co-ordinate the overall verification strategy
• Define and control verification management activities such asverification planning, verification tracking and reporting
• Control for work process compliance and high-quality verificationsign-off
• Define and implement Power aware simulation and Gate levelsimulations

You are best equipped for this task if you have:

• MS with 12+ years / BS with 14+ years
• Candidate should have strong background in digital verification usingSystem Verilog and UVM. 
• Should have developed multiple verificationenvironments for complex IP’s and SoC’s. 
• Should be capable ofdefining verification architecture for new IP’s and should havedeveloped verification environments.
• Candidate should have worked on ARMbased SoC verification covering RTL, Power Aware and Gate levelsimulations.
• Exposure to deployment of automation and formalverification methodologies is a plus.

#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in?

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