Principal Chip Verification Engineer

Execute SoC verification tasks and work closely with team members toreview and understand the relevant functional and safety-relatedrequirements.

Job Description
In your new role you will:

• Execute SoC verification tasks and work closely with team members toreview and understand the relevant functional and safety-relatedrequirements.
• Write verification plans to meet these requirements after closealignment with other verification teams for proper work split accordingto mutually acceptable verification assignment.
• Execute the verification plan by developing C/C++ test cases andSystem Verilog/UVM test bench components and by integrating 3rd partyVIP components.
• Simulate and debug at RTL, Unit Delay, and Gate Level usingappropriate tools and flows including Emulator, Portable Stimulus, orFormal methodologies for functional and toggle coverage closure.
• For a more senior role, you will also
• Lead a team technically through exploring new environment andidentifying potential enhancement areas through new methodology.
• Identify and setting mid/long term goals based on benchmarking againstindustry standards.

Your Profile
You are best equipped for this task if you have:

• Masters/Bachelors in Electrical Engineering or Computer Science with 15+years of relevant work experience.
• Strong foundational knowledge of digital design & verification.
• Advanced knowledge and hands-on experience of System Verilog and UVM.
•  Hands-on experience in hardware-software debugging at the system orapplication level. Hand-on experience with gate-level-simulations andwith debugging/troubleshooting skills is a plus
• Exposure to version-controlling (eg, Git/Bitbucket, ClearCase, CVS,SVN) and bug-management schemes
• Dynamic and energetic with zero verification escape mindset
• Self-motivated, flexible, good communication with interpersonal skillsand is a good team player who is able to work well with both internaland external partners.
• Candidate has proven ability to achieve results in a very dynamic,multi-site environment and be able to coordinate with priorities andself-initiatives.
• Knowledge on ISO26262 and ISO21434 are advantageous.
• Verification experience in COM, CPU peripherals, BUS or patterndevelopment is a plus. Experience in test bench/verification environmentset up is also a plus.

Contact:
    Gowri Shenoy [email protected], LinkedIn

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