PMU Analog Layout Engineer (m/f/d)

Will you help us design future generations of revolutionary Apple products? The Silicon Engineering team is seeking an Analog Layout Engineer with a strong foundation in custom analog layout and a real passion for building new technologies. At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary Layout Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. You will be responsible for the Layout and verification of Analog IP and the support of top-level layout of Power Management products for battery operated portable devices. You will work with the most modern power management processes which enable best in class Apple processors and the latest Apple modems to get the power they need to deploy their full performances.

Description

- Detailed transistor level layout of analog circuit blocks
- Block level and top-level layout through full verification flow including DRC, LVS, PERC, EM/IR and DFM checking
- Co-work with designers on block level and top-level floor-planning including area and effort estimation
- Execute peer reviews for critical and major layout blocks
- Layout according to DFM rules
- Top-level layout integration and verification
- Schedule management and tracking

Minimum Qualifications

Bachelor's in Electrical Engineering or related field, alternatively equivalent work experience
Fluency in English language
Excellent interpersonal skills and ability to work with multi-functional teams

Preferred Qualifications

Several years of experience in custom analog layout with extensive knowledge on planar and preferably non-planar CMOS technologies
Capability to lead other layout engineers for top-level integration.
Knowledgeable on layout techniques for device matching, power routing and minimising parasitics
You understand issues of RC delay, electromigration, and cross capacitance
Experience with Power Management circuit layout would be an asset
Must recognise failure prone circuit and layout structures, dedicatedly work with circuit designer for best approach to problems
High level proficiency in interpretation of Calibre DRC, ERC, LVS, etc.
Knowledge of Mentor Graphics and Cadence layout tools
Understanding of IO/ESD and LUP
Scripting skills in PERL or SKILL are considered a plus, but not required