Place and Route Engineers- Multiple postions

Two95 International Inc.

Apply to this job
Petaling Jaya, Selangor, Malaysia on site Until 8/22/2026 3+ years exp H-1B sponsor history First posted March 27, 2025 Last posted March 27, 2025
Job description

Work closely with front end design engineers to translate RTL-to-GDSII. Responsible for all aspects of physical design and implementation. Participate in the efforts of establishing physical design methodologies and flow automation. Work on chip and block floorplan, power/ clock distribution, chip assembly, P&R, and timing closure. Implement and monitor Quality Assurance/Quality Control standards based on corporate guidelines in a project setting. Train/mentor new employees.

JOB DESCRIPTION/OTHER RECRUIREMENT:

  • Power planning, optimization, power grid and signal routing considering timing constraints.
  • Design floor planning, analogue and memory macro placement.
  • Place and route including timing closure.
  • Extraction of layout parasitics and SPEF/ SDF generation. Signal integrity tests.
  • Post-synthesis static timing analysis (STA) and post-layout STA.
  • Physical verification (DRC, ERC, LVS, ANTENNA rules).
  • Writing, running, optimization of scripts for above tasks.
  • Implement and monitor Quality Assurance/ Quality Control standards based on corporate guidelines in a project setting.
  • Have done multiple tape outs and proven record of designing complex ICs in state of the art CMOS process technologies and has successfully placed products into volume production, preferably multiple times.

Requirements

REQUIREMENT

  • At least 3-5 years professional experience in microelectronics physical implementation.
  • Good verbal and writing communication skills. Fabrication process variation impacts and performance.
  • Experience in low-power design techniques.
  • Good understanding of ERC, EMI rules and impact on final chip verification and cycle time reduction.
  • Ability to work in a team environment and participate in cross-functional activities.
  • Experience with the following tools:
    • Mandatory: Cadence RTL Compiler, SOC-Encounter/ EDIS, ETS, EPS. o
    • Desirable: Mentor Calibre/ Assura.
    Malaysians and Expats are welcome to apply.Candidates must be willing to travel abroadCandidates must be open for outsourcing to different locations apart from our primary locations ( Petaling Jaya and Penang)Candidates must be willing to submit 3 recent paystubs while submitting resume.
About this role

Summary

Designs and implements physical layout, ensures timing, power, and signal integrity for ICs.

Job title

Place and Route Engineers- Multiple postions

Experience level

3-5 years

Minimum experience

3+ years exp

Industry

electronics

Location requirements

Petaling Jaya, Malaysia; remote possible, willing to travel and relocate

Salary

Not specified

Visa sponsorship

H-1B sponsor history

Management role

No

Skills & keywords

Required skills

RTL CompilerSOC-EncounterEPScadence

Preferred skills

CalibreAssurascript optimization

Specializations

physical designIC designplace and routetiming closurepower planning
Locations

Structured locations inferred from the posting.

Petaling Jaya, Selangor, Malaysia

On-site City

Malaysia

Remote Country