Physical Design Engineer

Current Openings

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Frisco, TX Until 8/22/2026 5+ years exp First posted April 18, 2026 Last posted April 18, 2026
Job description

About Talent 101 Inc

Talent 101 is an Engineering and IT services provider, with clients that range from start-up to Fortune 500. We specialize in solutions for the Semiconductor, Automotive, Electronics, Energy, Telecom, and Defense industries.

About the role

  • This is a full time position with our company doing Physical Design Engineering.

What you'll do

  • Lead end to end Physical Design from floorplan to GDS
  • Own full PnR flow: placement, CTS, routing, optimization, ECOs
  • Run, debug, and close DRC/LVS for foundry clean signoff
  • Drive timing closure using Tempus with strong constraint ownership
  • Perform synthesis and QoR optimization using Genus
  • Improve PPA across block level and IP level designs
  • Partner with internal IP teams to prepare blocks for tapeout readiness
  • Deliver signoff reports and support final tapeout package creation
  • 5+ years’ Physical Design experience
  • Strong hands on proficiency with Cadence Innovus, Tempus, and Genus
  • Proven success supporting internal IP tapeout
  • Ability to collaborate across RTL, verification, and integration teams


Talent101 pays referral fees.

Applicants must be at least 18 years or older, must be willing to take a drug test and background check as part of the selection process and must have legal authorization to work in the United States.

Talent 101 is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to protected characteristics, including race, color, religion, sex, national origin, disability, veteran status, sexual orientation, gender identity or age.

About this role

Summary

Lead end-to-end physical design from floorplan to tapeout, support signoff and optimize design process

Job title

Physical Design Engineer

Experience level

5+ years

Minimum experience

5+ years exp

Industry

semiconductor

Location requirements

must be in or willing to work remotely from Frisco, TX

Salary

Not specified

Management role

No

Skills & keywords

Required skills

Cadence InnovusTempusGenusDRC/LVSsignoff

Preferred skills

internal IP tapeout supportcollaboration with RTL and verification teams

Specializations

physical designplace and routetiming closurePPA optimizationtapeout support
Locations

Structured locations inferred from the posting.

Frisco, TX, USA

On-site City