Physical Design Engineer

Mirafra Technology

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San Diego, CA, us on site Until 8/21/2026 H-1B sponsor history First posted March 27, 2025 Last posted March 27, 2025
Job description

Mirafra is a global product engineering services company with expertise in semiconductor design, embedded and application software.

Job Overview:

The Graphics team is looking for Experienced Physical Design Engineers to work on Adreno Graphics cores in the area of Physical Implementation.

Responsibilities:

The Physical Implementation Engineer will work in Qualcomms Adreno GPU team and will be responsible for all the P&R experiments targeted at validating new flows/methodologies.

Minimum Qualifications:

Able to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing closure Must be
able to take the Hardmacro through P&R from Netlist to GDS including timing closure, formal and Physical verification.

Tools: EDA Physical design tools experience ( Examples: Cadence Innovas, Synopsys ICC2,  PrimetimeSi/Calibre/ etc)


Skills:

Physical design implementation expertize in latest technology nodes in one of the below domains or all of these.


1.Floor planning at Full chip level or Macro or Block Level

a.Macro placement, power grid implementation, power routing, special routing like analog signals etc

b.Power collapse/Low power implementation flow

2.P&R:
Place and route at chip level or block level, perform placement, timing closure in P&R mode, perform clock tree synthesis , routing etc

3.Timing closure/STA

a.Perform STA using primetime Si or Tempus or any industry standard STA engine, timing closure, ECO generation, timing correlation

b.Deep understanding of timing skills to perform correlation, timing fixes , corner/voltage definetions etc

4.Clock Tree Synthesis:

a.Perform custom or regular clock tree implementation at block level or top level.

b.Clock tree balance of complicated tree, clock power reduction techniques etc

5.Low Power Implementation

a.Power collapse/power gaing techniques/implementation

b.UPF/CPF flow knowledge

c.CLP/FV

6. Physical Verification Using Calibre a.Running all the PV checks (DRc/LVS/ERC/Softcheck ) and deep understanding of all the rules and fixes
7. Perl/Python/Shell script experience is also preferred to help with automation


All your information will be kept confidential according to EEO guidelines.

About this role

Summary

Design and implement physical design for GPU cores, perform timing closure and verification

Job title

Physical Design Engineer

Experience level

not specified

Industry

semiconductor

Location requirements

San Diego, CA, US; on-site preferred

Salary

Not specified

Visa sponsorship

H-1B sponsor history

Management role

No

Skills & keywords

Required skills

EDA toolsphysical designfloor planningplace and routetiming closureclock tree synthesiscalibreperlpython

Preferred skills

automation scriptingpower managementUPF/CPF

Specializations

physical designP&Rtiming closureclock tree synthesislow power
Locations

Structured locations inferred from the posting.

San Diego, CA, USA

On-site City