Physical Design Engineer

Cerebras Systems

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Sunnyvale, CA Until 8/22/2026 10+ years exp First posted June 11, 2026 Last posted June 11, 2026
Job description

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.  

Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. 

Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

About The Role

As a member of our tight knit physical design team, you will be working on the design and analysis of 3D integrated products. This role involves a combination of traditional ASIC/SoC physical design skills, packaging, power, clock and cooling analysis. You will work closely with the architecture and RTL team to do R&D on novel concepts for 3D integration. 

Skills and Qualifications

Required 

  •     10+ years of physical design/verification experience. 
  •     Strong knowledge of block level and full-chip physical verification methodology. 
  •     Expert at optimizing for the best power/performance and area.
  •     Experience with the complete physical design flow. Knowledge of Synopsys tool suite is a plus. 
  •     Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues. 
  •     Expert with IR/EM analysis and resolution.
  •     Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements. 
  •     Demonstrated ability to work with RTL teams to optimize for physical design.
  •     Knowledge of 2.5D or 3D packaging solutions.
  •     Must have experience with 3d physical design, 3d die stacking, 3d chip design, die-to-die or wafer-to-wafer.

Preferred    

  •     Experience doing full chip floor planning and integration.   
  •     Knowledge of clock distribution.
  •     Knowledge of cooling analysis.
The salary range for this position is $230,000 – $280,000 annually. Actual compensation will be determined based on factors such as experience, skills, qualifications, and location.
 

Why Join Cerebras

People who are serious about software make their own hardware. At Cerebras we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection  point in our business. Members of our team tell us there are five main reasons they joined Cerebras:

  1. Build a breakthrough AI platform beyond the constraints of the GPU.
  2. Publish and open source their cutting-edge AI research.
  3. Work on one of the fastest AI supercomputers in the world.
  4. Enjoy job stability with startup vitality.
  5. Our simple, non-corporate work culture that respects individual beliefs.

Read our blog: Five Reasons to Join Cerebras in 2026.

Apply today and become part of the forefront of groundbreaking advancements in AI!


Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.


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About this role

Summary

Design and verify 3D integrated products, optimize power/performance/area, work with RTL teams.

Job title

Physical Design Engineer

Experience level

10+ years

Minimum experience

10+ years exp

Industry

software

Location requirements

Sunnyvale, CA, on-site role, possibly hybrid

Salary

$230k–$280k

Management role

No

Skills & keywords

Required skills

physical designverificationpower optimizationSynopsysICVCalibreDRCLVSIR analysisEM analysisTclPythonRTL collaboration3D packagingdie stacking

Preferred skills

full chip floor planningclock distributioncooling analysis

Specializations

ASIC design3D integrationpackagingpowerthermal
Locations

Structured locations inferred from the posting.

Sunnyvale, CA, USA

On-site City