Package Integration Engineer

Looking for a senior level IC packaging engineer to develop exciting new products. You will be responsible providing Custom Silicon packaging solutions in a module/system for various consumer markets.

Description

• In this fast-paced environment, your role is to interface between internal product/device design, quality, supply chain, and the external suppliers to develop and deploy new packaging technologies.
• We are looking for individuals who are very innovative with a proven track record to

Minimum Qualifications

BS and 10+ years of relevant industry experience.

Preferred Qualifications

M.S or Ph.D. degree in mechanical engineering, physics, materials science or similar disciplines with a minimum of 10 years of experience in IC packaging. AutoCAD, APD and multi-physics simulation knowledge is a plus.
Some hands-on knowledge in Wafer Bumping, Manufacturing assembly processes; such as wafer back-grind, wafer dicing, Flip Chip die attach (including multilayer thin die stacking), encapsulation/molding, under-fill, ball attach, package singulation and Tape & Reel.
In-depth knowledge in Wafer Level Chip Scale Packaging (RDL/Wafer Bumping & BEOL Assembly processes for Fan-In & Fan-Out designs).
Expert level knowledge of common reliability failure modes. Able to understand device physics and component/board level reliability testing.
Proven track record to bring a product/package from conceptual stage to development and to HVM environment.
Ability to construct Designs of Experiments and down-select materials and processes.
Good written and verbal communication skills. Able to present ideas, design concepts, data and plan with high confidence at team meetings and executive review meetings.
Able to perform independent research and development work with minimal supervision.