Package Design Engineer

Broadcom Corporation

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US-CA San Jose Innovation Drive US-TX-Austin - River Place B7 Until 9/30/2026 6+ years exp H-1B sponsor history First posted August 1, 2026 Last posted August 1, 2026
Job description

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Job Description:

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team.

RESPONSIBILITIES:

  • Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.

  • Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.

  • Schedule, prioritize, & track your work across 2+ projects simultaneously

  • General flip-chip BGA package design & engineering

  • Project management and customer interface for your design projects

  • Contribute to efficiency improvements for the design team, through process development/improvement, automation, documentation, etc.

  • Physical design (layout) is a foundational responsibility in this role

 
EDUCATION/EXPERIENCE & REQUIREMENTS:

  • BSEE or similar field and 8+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 6+ years’ work experience

  • Knowledge of package-level signal integrity and power integrity, to apply to package designs

  • Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.

  • Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers

  • Self-management and organization skills

  • Preferred candidates will also have 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest

OTHER REQUIREMENTS

  • This job requires working on-site at the Broadcom office, 5 days a week. This is not a remote-work position.


Compensation and Benefits


The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

About this role

Summary

Designs and manages ASIC package structures focusing on signal, power, and thermal aspects.

Job title

Package Design Engineer

Experience level

8+ years or 6+ years with MSEE

Minimum experience

6+ years exp

Industry

technology

Location requirements

On-site in USA at specified locations, no remote work allowed.

Salary

$122k–$195k

Visa sponsorship

H-1B sponsor history

Management role

No

Skills & keywords

Required skills

flip-chip-BGAsignal integritypower integrityCadence APD

Preferred skills

Cadence SKILLdesign automation coding

Specializations

flip-chip-BGAsignal integritypower integrityautomated design
Locations

Structured locations inferred from the posting.

San Jose, CA, USA

On-site City

Austin, TX, USA

On-site City

Fort Collins, CO, USA

On-site City