Modem Bus Interconnect Verification Engineer

This role is for one of the Weekday's clients

Min Experience: 4+ years

Location: Bengaluru, Karnataka, India

JobType: full-time

We are seeking a skilled Modem Bus Interconnect Verification Engineer to join our SoC verification team. In this role, you will be responsible for verifying modem bus interconnects and ensuring reliable communication across complex SoC subsystems. You will develop robust verification environments, execute comprehensive verification plans, and collaborate closely with Design, Architecture, and Validation teams to deliver high-quality silicon.

Requirements

Key Responsibilities

• Develop and execute verification plans for modem bus interconnects and SoC subsystems.
• Build and maintain SystemVerilog/UVM-based verification environments for AMBA bus protocols.
• Verify bus interconnect functionality, connectivity, arbitration, performance, and protocol compliance.
• Develop constrained-random test cases, assertions, and functional coverage models to achieve verification closure.
• Perform assertion-based verification (SVA) to validate protocol behavior and design correctness.
• Debug RTL and simulation failures using industry-standard simulators such as VCS, Xcelium, or Questa.
• Analyze functional coverage metrics and drive closure by identifying verification gaps.
• Collaborate with Design, Architecture, Physical Design, and Firmware teams to resolve functional issues.
• Develop automation scripts using Perl, Python, or Shell to improve verification efficiency.
• Participate in design and verification reviews while contributing to verification methodology improvements.

Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline.
• 4–6 years of experience in SoC or Modem Verification.
• Strong understanding of AMBA protocols, including AXI, AHB, and APB.
• Hands-on experience with SystemVerilog and UVM.
• Proven experience in Bus Interconnect Verification.
• Strong knowledge of constrained-random verification methodologies.
• Experience with functional coverage and SystemVerilog Assertions (SVA).
• Good debugging skills using VCS, Xcelium, or Questa simulators.
• Exposure to Perl, Python, or Shell scripting for automation.
• Strong analytical, debugging, and problem-solving skills.
• Excellent communication and collaboration abilities.

Must-Have Skills

• Modem Bus Interconnect Verification
• SoC Verification
• AMBA Protocols (AXI, AHB, APB)
• SystemVerilog
• UVM
• Constrained-Random Verification
• Functional Coverage
• SystemVerilog Assertions (SVA)

Good-to-Have Skills

• Bus Interconnect Verification
• VCS
• Xcelium
• Questa Simulator
• Perl
• Python
• Shell Scripting
• Verification Automation
• RTL Debugging
• ASIC/SoC Verification