Mixed Signal Design Verification Engineer - Early Career (m/f/d)

At Apple, we work every day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? The Silicon Engineering team in Livorno is seeking a forward-thinking and innovative Mixed Signal Design Verification Engineer with a solid foundation in AMS Verification processes and a real passion for building new technologies. In this role, you will be responsible for the Analog Mixed Signal Design Verification of Power Management Units for portable devices.

Description

You will work within the Analog Mixed Signal Design Verification Team with experienced Verification Engineers, in order to achieve top-level mixed signal verification with the highest quality, efficiency, and time-to-market. You will focus on system requirements and collaborate with the architecture, analog, digital, and software teams to ensure specification compliance and accurate functionality. You will develop comprehensive verification test plans that exploit analog, digital and mixed signal verification environments to guarantee that potential issues are addressed early in the design cycle. You will design and implement test benches, models at different abstraction levels, high-coverage stimulus vectors, tools, monitors and checkers to verify the target performance. You will follow a collaborative approach to communicate status and results to multiple subject areas in an international context, and you will partner closely with CAD and verification methodology groups.

Minimum Qualifications

Master’s in Electrical Engineering or equivalent field required
Analog and digital design background that supports the analysis of verification results
Knowledge of scripting languages (Python/Perl/TCL)
Teammate with excellent written and verbal communication skills, always enthusiastic to collaborate with international teams
Experienced engineers with several years of industry experience or graduates with outstanding academic results and relevant internship experiences are considered

Preferred Qualifications

Experience in behavioral modelling using System Verilog and Verilog AMS, targeting analog, digital or mixed signal verification environments
Knowledge of UVM, Assertion Based Verification, Functional Coverage, Formal Verification
Understanding of AI and ML and their potential application to verification
Hands on experience in mixed signal verification using state-of-the-art EDA tools