Memory Packaging Engineer

Santa Clara Until 9/22/2026 3+ years exp First posted July 24, 2026 Last posted July 24, 2026
Job description

Join the team at the heart of memory innovation for every Apple product. As a Memory Packaging Engineer, you will architect the memory solutions that power the industry-leading performance of Apple's hardware. We push the boundaries of bandwidth density, power efficiency, and system integration through meticulous co-design between memory technology and our world-class systems. If you are driven to solve the industry's toughest packaging challenges, your work will have a profound and lasting impact on the products used by millions.

Description

In this role, you will drive the definition, development, and qualification of next-generation memory packages critical to Apple’s future products.
You will guide the package roadmaps of our memory partners and collaborate with internal engineering teams to enable bandwidth and density scaling.
Your ownership will span the entire product lifecycle, from initial concept through qualification.

Minimum Qualifications

Minimum requirement of a bachelor's degree in a relevant field

Preferred Qualifications

MS or PhD preferred, with 3+ years of industry experience in package design and assembly process development of high-bandwidth and high-density memory packages.
Strong knowledge of thin-die stacking technologies including wirebond, flip-chip, and wafer/die bonding.
Strong knowledge of packaging materials and design to engineer warpage and CTE properties and mitigate thermal challenges.
Solid working experience in package test and reliability, system-level downstream process interaction, and packaging inspection metrology.
Deep understanding of SI/PI co-design with memory die and high-speed DDR or differential signaling.
Understanding of how memory die floorplan and architecture influence package structure and routing, with experience collaborating with memory die design teams.
Excellent communication skills for collaborating with internal teams and managing external vendors.

About this role

Summary

Designs and qualifies high-density memory packages; collaborates across teams.

Job title

Memory Packaging Engineer

Experience level

3+ years

Minimum experience

3+ years exp

Industry

technology

Location requirements

Santa Clara, on-site; remote not specified

Salary

Not specified

Management role

No

Skills & keywords

Required skills

package designassembly process developmentwirebondflip-chipwafer/die bondingthermal challengesreliability testingmetrologyDDR high-speed signalingmemory die architecture

Preferred skills

warpage controlCTE managementsystem-level interactioncollaborating with memory die design teamscommunication

Specializations

memory packaginghigh-bandwidthsystem integrationthermal mitigationSI/PI co-design
Locations

Structured locations inferred from the posting.

Santa Clara, CA, USA

On-site City