Memory Layout Design Engineer

Broadcom Corporation

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IND-Bangalore Electronic City - S1 Until 10/4/2026 3+ years exp H-1B sponsor history First posted August 5, 2026 Last posted August 5, 2026
Job description

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Job Description:

Job Requirements:
- Minimum 3 years of experience with strong layout knowledge
- Bachelor's degree required.
- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).
- Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).
- Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.
Job Description:
- Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
- Manage scheduling, timelines, and layout floor-planning.
- Responsible for start to end deliverables with quality within the planned schedule.
- Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.
Skill Set (Memory):
- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.
- Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.
- Proficiency in floor-planning, hierarchy layout, and chip integration.
- Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines
- Knowledge of AI, automation in layout, Script Programming and SKILL Programming is a plus.
- Ability to lead, train junior engineers, and manage projects effectively.
- Good knowledge of memory layout topology; experience with memory compilers is a plus.
- Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
- Self-reliant with the ability to work both independently and collaboratively.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

About this role

Summary

Design and verify memory layout, manage projects, and apply layout guidelines.

Job title

Memory Layout Design Engineer

Experience level

3+ years

Minimum experience

3+ years exp

Industry

semiconductor

Location requirements

Bangalore, India; on-site work only

Salary

Not specified

Visa sponsorship

H-1B sponsor history

Management role

No

Skills & keywords

Required skills

layout knowledgecadence toolscalibre verificationmemory layoutCMOS processes

Preferred skills

script programmingskill programmingmemory architectureautomation

Specializations

layout designmemorycadence toolssubmicron processesCMOS
Locations

Structured locations inferred from the posting.

Bengaluru, Karnataka, India

On-site City
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