Lead Design Engineer(Virtual Solution)

SHANGHAI Until 8/22/2026 3+ years exp First posted June 12, 2026 Last posted June 12, 2026
Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities

  • Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium)
  • Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation
  • Develop end-to-end verification flows including:
    • AVIP integration
    • Testbench and system modeling
    • Bare-metal / driver-level validation
  • Optimize solutions for performance, scalability, and emulation efficiency
  • Develop custom test cases, tools, and automation to enable advanced use models (embedded / co-emulation / hybrid flows)
  • Work closely with cross-functional teams (PE, AE, customers) to debug and resolve system-level issues
  • Support customer enablement, including bring-up, debug, and solution deployment

Required Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with at least 3 years’ experience
  • Strong expertise in high-speed protocols such as:
    • PCIe, CXL, AMBA, UCIe, Ethernet (at least one)
  • RTL design experience (SystemVerilog / Verilog)
  • C/C++ development experience for modeling, testbench, or system integration
  • Hands-on experience with Palladium / Protium / FPGA / emulation platforms is strongly preferred
  • Good debugging skills for complex system integration issues

Preferred Qualifications

  • Experience developing or using AVIP (Accelerated VIP) solutions
  • Experience with end-to-end system validation flows (simulation → emulation → prototyping)
  • Knowledge of UVM and verification frameworks
  • Knowledge of Qemu/Gem5 or other system emulation projects
  • Experience with multi-language environments (SV + C/C++ + Python)
  • Familiarity with Emulation/Prototyping flows
  • Exposure to AI/ML techniques applied to verification or tooling
  • Strong problem-solving skills and ability to work independently

Soft Skills

  • Excellent English communication skills (both verbal and written) are required.
  • Strong learning capability and adaptability to new technologies
  • Ability to collaborate across global teams
  • Proactive mindset in problem solving and customer engagement

We’re doing work that matters. Help us solve what others can’t.

About this role

Summary

Design high-speed emulation solutions, develop verification flows, and collaborate with international teams.

Job title

Lead Design Engineer(Virtual Solution)

Experience level

3+ years

Minimum experience

3+ years exp

Industry

software

Location requirements

Candidates in Shanghai or willing to relocate, remote possible

Salary

Not specified

Management role

No

Skills & keywords

Required skills

Electrical EngineeringComputer EngineeringPCIeCXLAMBAUCIeEthernetRTLSystemVerilogVerilogCC++Pythondebugging

Preferred skills

AVIPUVMQemuGem5multi-languageemulationprototypingAIML

Specializations

emulationverificationsystem modelinghigh-speed protocolsFPGA
Locations

Structured locations inferred from the posting.

Shanghai, China

Remote City