Lead Design Engineer
CADENCE US
Apply to this job PUNE Until 8/21/2026 First posted March 22, 2025 Last posted March 22, 2025
Job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
3++ Year ASIC Design / Verification experience. Required Expertise in PCIe / Storage (ONFI, XSPI, SD/eMMC) Design and Verification domain. Good debug skills and good communication skills.
We’re doing work that matters. Help us solve what others can’t.
About this role
Summary
Design and verify ASICs with expertise in PCIe and storage technologies.
Job title
Lead Design Engineer
Experience level
3+ years
Industry
technology
Location requirements
Located in Pune, remote work not allowed
Salary
Not specified
Management role
No
Skills & keywords
Required skills
ASIC DesignVerificationPCIeStoragedebugcommunication
Preferred skills
None specified
Specializations
ASICPCIeStorageVerificationDebug
Locations
Structured locations inferred from the posting.
Pune, Maharashtra, India
On-site City