Layout Designer
CADENCE US
Apply to this job Nanjing Until 8/22/2026 First posted March 22, 2025 Last posted March 22, 2025
Job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
工作内容:
- 负责模拟电路的版图设计、版图验证;
- 分析Foundry所提供的工艺流程和设计规则,理解所用工艺器件的平面和纵向结构;
- 与设计工程师充分沟通,确保完全理解设计对版图的要求。
要求:
微电子,半导体物理等本科及以上学历,有较好的集成电路工艺基础和模拟电路基础。 熟练使用Cadence virtuoso进行版图设计。 能主动积极完成各种版图设计任务。 很好的沟通能力和团队合作能力。
We’re doing work that matters. Help us solve what others can’t.
About this role
Summary
Design and verify layouts for analog circuits, ensuring design requirements are met.
Job title
Layout Designer
Experience level
entry level
Industry
semiconductor
Location requirements
Located in Nanjing, remote work not allowed
Salary
Not specified
Management role
No
Skills & keywords
Required skills
microelectronicssemiconductor physicsCadence virtuosocommunicationteamwork
Preferred skills
None specified
Specializations
layout designsemiconductorcommunicationteamwork
Locations
Structured locations inferred from the posting.
Nanjing, Jiangsu, China
On-site City