Junior DV

CZ61 NXP Semiconductors Czech Republic s.r.o.

Apply to this job
Catania Until 10/6/2026 2+ years exp H-1B sponsor history First posted August 7, 2026 Last posted August 7, 2026
Job description

As a Design Verification Engineer at NXP Semiconductors, you will play a crucial role in ensuring the functional correctness and quality of our cutting-edge semiconductor designs. You will be responsible for developing and executing comprehensive verification plans to validate complex digital circuits, contributing to the delivery of robust and reliable products.

Your Job Responsibilities

* Develop and implement efficient and comprehensive verification environments and test benches using industry-standard methodologies (e.g., UVM, SystemVerilog).

* Create detailed verification plans based on design specifications, identifying key functionalities and potential corner cases.

* Develop, execute, and debug test cases to thoroughly verify the design against its specifications.

* Analyze simulation results, identify discrepancies, and work closely with design engineers to resolve issues.

* Develop and maintain verification collateral, including assertions, functional coverage models, and verification scripts.

* Participate in verification reviews, contributing to the improvement of verification methodologies and processes.

* Collaborate with design, architecture, and software teams throughout the product development lifecycle.

* Contribute to the continuous improvement of verification flows and tools.

* Document verification strategies, test plans, and results effectively.

Your Profile

* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

* Proven experience (typically 2+ years) in digital IC design verification.

* Strong proficiency in SystemVerilog and UVM (Universal Verification Methodology).

* Experience with industry-standard simulation tools (e.g., Questa, VCS, Xcelium).

* Solid understanding of digital design principles and architectures.

* Experience with scripting languages such as Python, Perl, or Tcl.

* Familiarity with functional coverage driven verification and assertion-based verification.

* Excellent problem-solving skills and attention to detail.

* Strong communication and interpersonal skills, with the ability to work effectively in a team environment.

* Fluency in English, both written and spoken.


-----------

NXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.

As of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 31,200 € and 43,000 € annually. This range is intended as a guideline. Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs. This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria). Where relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package.

More information about NXP in Italy...

-----------

#LI-6710
About this role

Summary

Verify digital IC designs using SystemVerilog, UVM, and simulation tools; develop verification plans and testbenches.

Job title

Junior DV

Experience level

2+ years

Minimum experience

2+ years exp

Industry

semiconductors

Location requirements

Catania, Italy; remote work not mentioned

Salary

$31k–$43k

Visa sponsorship

H-1B sponsor history

Management role

No

Skills & keywords

Required skills

SystemVerilogUVMsimulation toolsPythonassertion-based verification

Preferred skills

None specified

Specializations

digital verificationSystemVerilogUVMsimulation toolsverification
Locations

Structured locations inferred from the posting.

Catania, Metropolitan city of Catania, Italy

On-site City