IC Packaging Engineer - WLP

San Francisco Bay Area Until 9/28/2026 10+ years exp First posted July 30, 2026 Last posted July 30, 2026
Job description

Do you like to work on groundbreaking technology? Have a passion for creating amazing products? Our team is looking for a hardworking, IC Packaging Engineer with strong attention for details and love for excellence and precision to accomplish extraordinary results. In this highly impactful role, you will initiate package concepts, own and drive sophisticated package selection, new product package structure and configuration optimization. You will be responsible for packaging integration and package technology development for a variety of projects including SoC.

Description

You'll drive package integration across SoC and advanced 2.5D / 3D packaging projects, from architecture trade-off studies through characterization, modeling, and product delivery. You'll manage process development and enable MP-ready packaging solutions on product, own complex technical deliverables end-to-end, and lead DOEs and build execution with foundry and OSAT partners. You'll also serve as a technical anchor across design, test, reliability, and product teams. We're looking for a seasoned engineer with deep packaging expertise, strong cross-functional and supplier partnership skills, and a solution-oriented mindset grounded in engineering physics.

Minimum Qualifications

BS and 10+ years of relevant industry experience or equivalent

Preferred Qualifications

MS or PhD in a relevant discipline, with a thesis or coursework in semiconductor packaging, materials, thermal, mechanical, or electrical modeling
Deep experience in the Semiconductor Packaging field, with a proven track record taking packages from concept to HVM
Established expertise in Wafer Level Packaging, 2.5D packaging, and 3D packaging technology.
Strong knowledge in materials characterization and analysis.
Broad understanding of packaging technologies, assembly processes, IC packaging materials, reliability standards, and FA techniques.
Proven experience with package design software (APD, Virtuoso, or equivalent).
Demonstrated experience in memory packaging.
Excellent interpersonal skills, with a track record of strong business partnerships and cross-functional collaboration, including overseas suppliers.
Ability to work independently and orchestrate complex, multi-team projects with minimal supervision.
Solution-oriented engineer with proven fundamentals in engineering physics.
Strong program management skills.

About this role

Summary

Manage packaging integration, develop solutions for advanced SoC and WLP projects.

Job title

IC Packaging Engineer - WLP

Experience level

10+ years

Minimum experience

10+ years exp

Industry

semiconductors

Location requirements

San Francisco Bay Area, no remote work allowed.

Salary

Not specified

Management role

No

Skills & keywords

Required skills

semiconductor packagingpackage design softwarematerials characterizationpackage integration

Preferred skills

wafer level packagingmemory packagingcross-functional collaborationprogram management

Specializations

package integration2.5D packaging3D packagingsemiconductor packagingmaterials characterization
Locations

Structured locations inferred from the posting.

Unknown location

On-site