IC Layout Engineer

Broadcom Corporation

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Singapore-Yishun Until 9/30/2026 2+ years exp H-1B sponsor history First posted August 1, 2026 Last posted August 1, 2026
Job description

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Job Description:

Role Overview
Responsible for executing high-quality layouts across Standard Cells, I/O pads, and Mixed-Signal IP in advanced processes within project schedules.
Key Responsibilities
  • Layout Design & Execution: Apply design guidelines and advanced process rules to deliver high-performance, robust layouts.
  • Planning & Floorplanning: Manage schedule and execute layouts from the transistor level up including cell- and block-level floorplanning.
  • Collaboration: Adopt new methodologies, communicate actively across sites, and work closely with senior layout engineers.
Skill Set & Requirements
  • Education & Experience:
    • Bachelor’s Degree in Electronic Engineering.
    • 2 to 3 years of hands-on IC layout experience
  • Technical Skills:
    • Solid grasp of Standard Cell, Memory, or Analog/Mixed-Signal layout basics.
    • Familiarity with basic ESD/Latch-up layout techniques and transistor-level placement.
    • Practical experience with physical verification: DRC, LVS, ERC, and Antenna checks.
    • Basic understanding or exposure to sub-micron or advanced process nodes (e.g. 5nm, 3nm, 2nm, 1.4nm ).
  • Tools & Concepts:
    • Proficient with Cadence Virtuoso layout tool and Calibre physical verification (DRC, LVS, ERC, Antenna, and EM/IR analysis.)
    • Scripting knowledge (Shell, Python, Tcl) or Cadence SKILL programming in a plus.
  • Personal Attributes: Quick learner, proactive, team player, with good communication and strong problem-solving skills.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

About this role

Summary

Designs and verifies IC layouts using Cadence tools for advanced nodes.

Job title

IC Layout Engineer

Experience level

2-3 years

Minimum experience

2+ years exp

Industry

semiconductor

Location requirements

Yishun, Singapore; on-site work required

Salary

Not specified

Visa sponsorship

H-1B sponsor history

Management role

No

Skills & keywords

Required skills

layout designverifications (DRC, LVS, ERC)cadence virtuosocalibrescripting (Shell, Python, Tcl, SKILL)

Preferred skills

advanced process nodestransistor-level placementAntenna checks

Specializations

layout designphysical verificationprocess nodescadence virtuosocalibre
Locations

Structured locations inferred from the posting.

Yishun, Singapore

On-site City