IC Design Engineer
Broadcom Corporation
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Job Description:
Key DFT Responsibilities & Skills:
- Tool Expertise: Extensive experience with the Siemens Tessent tool suite.
- DFT Architecture & Integration: Responsible for top-level DFT planning and integration.
- ATPG & ATE: Managing the ATPG (Automatic Test Pattern Generation) and ATE (Automated Test Equipment) interface, including ATE bring-up and failure analysis.
- Test Optimization: Driving test time reduction strategies.
- Synthesis & Verification: Handling synthesis, formal verification, and performing STA (Static Timing Analysis) & Simulation specifically for DFT modes.
- Power Domain Management: Implementing DFT across multi-power domain designs.
- Methodology & Support: Troubleshooting DFT-related issues and continuously driving DFT flow improvements.
Education & Experience:
Bachelors and 12+ years of related experience; at this level a post-graduate degree is typically expected or Masters degree and 10+ years of related experience
Compensation and Benefits
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Summary
Designs and verifies integrated circuit DFT incorporating Siemens Tessent tools.
Job title
IC Design Engineer
Experience level
12+ years
Minimum experience
12+ years exp
Industry
semiconductors
Location requirements
On-site in San Jose, CA, USA, with remote work not specified.
Salary
$144k–$230k
Visa sponsorship
H-1B sponsor history
Management role
No
Required skills
Preferred skills
Specializations
Structured locations inferred from the posting.
San Jose, CA, USA