Graduate Talent (Design Verification Engineer)

Intel Corporation

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Malaysia, Penang Malaysia, Kulim Until 9/27/2026 0+ years exp First posted July 29, 2026 Last posted July 29, 2026
Job description

Job Details:

Job Description: 

The Role and Impact Join our dynamic team dedicated to developing cutting-edge PCIe Controller IPs, driving the future of high-speed I/O interfaces. As part of this innovative environment, you will play a critical role in ensuring the functionality and performance of advanced IP logic designs that meet and exceed specification requirements. Your contributions will directly impact the development of groundbreaking technologies, shaping Intel's success in the competitive technology landscape. Key Responsibilities - Develop and execute functional verification plans to ensure IP logic designs meet microarchitecture specifications. - Create and maintain test benches and verification environments, implementing methodologies such as OOP/OVM/UVM and System Verilog Testbench. - Perform system simulations to analyze power, timing, and functionality, identifying and debugging issues in the pre-silicon environment. - Collaborate with architects, RTL developers, and physical design teams to optimize verification processes and resolve complex technical challenges. - Root cause, debug, and implement corrective measures for failing test cases. - Contribute to improving and maintaining functional verification infrastructure and methodologies. - Document test plans, verification strategies, and results, participating in technical reviews with cross-functional teams. - Stay updated on the latest IP technologies and bring innovative approaches to the verification process.

Qualifications:

Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. - Proficiency in hardware description languages (HDLs) such as Verilog or VHDL, and System Verilog Testbench. - Foundational understanding of digital design principles and verification methodologies. - Knowledge of verification tools like ModelSim or Synopsys VCS. - Strong analytical and debugging skills, with a problem-solving mindset. Preferred Qualifications - Prior experience, internships, or academic projects in IP development or verification. - Familiarity with advanced verification methodologies, such as UVM, OVM, or similar frameworks. - Proven ability to collaborate within diverse teams, demonstrating strong communication and teamwork skills. - Motivation to learn, adapt, and contribute to fast-evolving technologies and environments. We are excited about the potential impact you can make and look forward to seeing how your skills and passion align with our mission to innovate and excel. Take the next step in your career journey with us today. Apply now to be a part of our team driving the future of technology.

          

Job Type:

Intel Contract Employee

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Malaysia, Kulim

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About this role

Summary

Develop and execute verification plans for IP logic designs, collaborating with cross-functional teams.

Job title

Graduate Talent (Design Verification Engineer)

Experience level

entry level

Minimum experience

0+ years exp

Industry

technology

Location requirements

On-site in Malaysia, Penang or Kulim, no remote work

Salary

Not specified

Management role

No

Skills & keywords

Required skills

VerilogVHDLSystemVerilog TestbenchModelSimSynopsys VCS

Preferred skills

UVMOOPVerification methodologiesTeam collaboration

Specializations

verificationhardware description languagesUVMSystemVerilogIP development
Locations

Structured locations inferred from the posting.

George Town, Penang, Malaysia

On-site City

Kulim, Kedah, Malaysia

On-site City