Education

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

• Coursework or projects in VLSI, Digital Design, and Computer Architecture.

Technical Skills

RTL Design & Hardware Description Languages

• Basic experience with Verilog or VHDL for digital design.

• Understanding of combinational & sequential logic, finite state machines (FSMs), and pipeline architectures.

Simulation & Verification Basics

• Exposure to testbenches, functional simulation using ModelSim, VCS, or Xcelium.

• Basic understanding of SystemVerilog assertions (SVA) and testbenches.

• Awareness of UVM (Universal Verification Methodology) is a plus.

Synthesis & Timing Analysis (Preferred)

• Basic knowledge of synthesis flow (Design Compiler, Genus, or Vivado).

• Understanding of setup/hold timing violations and static timing analysis (STA).

Scripting & Automation

• Basic understanding of AMBA protocols (AXI, AHB, APB).

• Awareness of memory subsystems, clock domains, and reset strategies.

• Exposure to industry standards like PCIe, USB, DDR, or MIPI is a plus.

Experience & Projects

• Internships or academic projects related to RTL design, FPGA prototyping, or digital system design.

• Hands-on experience in FPGA-based projects using Xilinx or Intel FPGA tools is an advantage.

Soft Skills

• Problem-solving: Ability to debug design issues.

• Communication: Ability to document designs and discuss technical topics clearly.

• Collaboration: Willingness to work with verification and backend teams.