Engineer - Digital Verification

Hanoi (Vietnam) Until 8/21/2026 H-1B sponsor history First posted July 15, 2025 Last posted July 15, 2025
Job description
We're seeking a Digital Verification Engineer who will champion the verification of digital designs, grasp requirements and specifications, and lead the development of test plans and test benches.

Job Description
In your new role you will:
  • Be responsible for the verification of digital designs
  • Be able to understand requirements & specifications
  • Focus on Test plan and test bench development
  • Be responsible for IP verification (Formal, SystemVerilog, UVM)
  • Support the Flow & Methodology improvements


Your Profile
You are best equipped for this task if you have:
  • Degree in Electronic or Computer Engineering
  • 0-3 years of industry experience in Digital Verification
  • Development of verification environments and methodologies at block subsystem level
  • Extensive knowledge of SystemVerilog / Verilog / UVM / VMM
  • Fluency in English




Contact:
    [email protected]

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About this role

Summary

Verify digital designs and develop test plans and benches.

Job title

Engineer - Digital Verification

Experience level

0-3 years

Industry

semiconductors

Location requirements

Located in Hanoi, Vietnam; remote work not allowed.

Salary

Not specified

Visa sponsorship

H-1B sponsor history

Management role

No

Skills & keywords

Required skills

degree in electronic engineeringdigital verificationverification environmentssystemverilogveriloguvmvmmenglish

Preferred skills

None specified

Specializations

digital verificationtest plantest benchIP verificationmethodology
Locations

Structured locations inferred from the posting.

Hanoi, Vietnam

On-site City