Digital Verification Engineer
Mindlance
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· 3years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.
· Extensive hand on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage, assertions (SVA), simulations, regression, debug, bug reporting/tracking.
· Experience in debugging RTL & Gate level simulations
· Part of multiple tapeouts with high quality verification.
· Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience
To discuss on this opportunity feel free to reach Praveen and My Number is 732-630-6121. Thanks
Summary
Verify digital blocks using SystemVerilog, UVM, and debugging RTL and gate level simulations.
Job title
Digital Verification Engineer
Experience level
3+ years
Industry
software
Location requirements
On-site in San Diego, CA, no remote work allowed.
Salary
Not specified
Management role
No
Required skills
Preferred skills
Specializations
Structured locations inferred from the posting.
San Diego, CA, USA